The present invention relates generally to digital computers and processors and, in particular, is directed to methods and apparatus for executing instructions for manipulating digital data.
Digital video technology is increasingly being incorporated into consumer electronic equipment. This video technology is superior to the analog video technology now used in commercial broadcasting and traditional VCRs because it provides improved picture quality and increased editing flexibility. Conventional digital video signals, however, require undesirably wide channels for transmission and undesirably large amounts of memory for storage. To avoid these problems, digital video signals are often "compressed" prior to use thereby making possible advances such as digital broadcast television, digital satellite television, video teleconferencing, and video mail.
Digital video signal compression reduces the amount of data by removing redundant information from the signal, thereby reducing the amount of data without affecting the quality of an image produced from the decompressed signal. A video signal processor that performs both compression and decompression of video signals is known as a "codec." FIG. 1 is a basic flow diagram showing data compression ("encoding") and data decompression ("decoding") processes of a prior art codec. For more information regarding the operation of a standard codec, see Stephen J. Solari, Digital Video and Audio Compression (1997), pp. 51-76.
Codecs typically employ some type of computer processor to perform the functions of compression and decompression. Conventional computer central processing units (CPUs) known as "complex instruction set computer" (CISC) processors are characterized by the capability to perform many different types of computer instructions. In particular, CISC processors can perform memory-to-memory instructions with complex memory accesses. In the past, CPUs could execute instructions faster than memory circuits could store or retrieve data. Thus, the complex instructions of CISC processors were used in place of software subroutines, thereby reducing the time that the CPU spent waiting for the memory to deliver instructions and enhancing computer performance.
With increasing memory speeds, however, computer designers have developed "reduced instruction set computer" (RISC) processors that take advantage of the nuances of high-level languages and specially designed hardware architectures. As the name implies, RISC processors use fewer types of instructions than CISC processors. RISC processors achieve high performance by implementing the most common computer instructions directly in hardware, usually at an execution rate of one instruction per clock cycle. Tasks too complex to execute in a single cycle are implemented by programmers by using a series of basic instructions inserted into high-level language instructions ("in-line code") or by calling a subroutine. For more information on RISC processors, see Kane et al., "MIPS R2000 RISC Architecture", Prentice Hall, 1992.
RISC architectures also gain speed by "pipelining," that is, overlapping the execution of instructions which require more than a single clock cycle. In pipelining, instructions that are executed multiple times in a row are divided into discrete portions each requiring one clock cycle and executed in parallel. When the first discrete portion of the first instruction finishes, the second instruction begins execution. With pipelining, each instruction takes the same amount of time to complete, but the overall rate of execution of the instruction set improves.
Designers of special purpose devices, such as, for example, codecs, have incorporated RISC processors into their products to improve performance. The designers often optimize the performance of particular products by extending the normal instruction set of a RISC processor with a set of instructions that are executed repeatedly by a special purpose application program. The present invention provides methods and apparatus for performing bit manipulation that enhance the performance of computer processors by increasing speed. The present invention also provides methods and apparatus for performing bit manipulation that, in particular, improve the performance of digital video codecs.